GBA Instruction Set

ARM

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Thumb

adcs  Rd, Rs
// Rd = Rd + Rs + C-bit

Description

Add contents of Rd, the contents of Rs, and the C-bit of the CPSR. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows adc for this instruction

ARM Equivalent

adcs Rd, Rd, Rs

Example

adcs r0, r3  // r0 = r0 + r3 + C-bit and set condition
             // codes on the result.
add   sp, #Value
// sp = sp + Value

Description

Add 9-bit immediate value to contents of sp and place the result in sp.

Notes

  • Does not set CPSR condition codes
  • Value must range from 0 to 508, word aligned
  • Assembler also allows for this instruction:
    • sub sp, #-Value

ARM Equivalent

add sp, sp, #Value

Example

add sp, #64  // sp = sp + 64
add   Rd, Rs
// Rd = Rd + Rs

Description

Add contents of Rd to contents of Rn. Place result in Rd.

Notes

  • Does not set CPSR condition codes
  • Rd and Rs can range from r0 to r15, unlike most Thumb instructions
  • Either Rd or Rs (or both) must range from r8 to r15

ARM Equivalent

add Rd, Rd, Rs

Example

add r0, r12  // r0 = r0 + r12
add   Rd, Rs, #Value
// Rd = Rs + Value

Description

Add 10-bit immediate value to contents of Rs. Place result in Rd.

Notes

  • Does not set CPSR condition codes
  • Rd must range from r0 to r7
  • Rs must be sp or pc
  • Value must range from 0 to 1020, word aligned

ARM Equivalent

add Rd, Rs, #Value

Example

add r0, sp, #212  // r0 = sp + 212
adds  Rd, #Value
// Rd = Rd + Value

Description

Add 8-bit immediate value to contents of Rd and place the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd must range from r0 to r7
  • Value must range from 0 to 255
  • Assembler also allows add for this instruction

ARM Equivalent

adds Rd, Rd, #Value

Example

adds r1, #255  // r1 = r1 + 255 and set condition codes
               // on the result.
adds  Rd, Rs
// Rd = Rd + Rs

Description

Add contents of Rd to contents of Rn. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows add for this instruction

ARM Equivalent

adds Rd, Rd, Rs

Example

adds r0, r3  // r0 = r0 + r3 and set condition codes on
             // the result.
adds  Rd, Rs, #Value
// Rd = Rs + Value

Description

Add 3-bit immediate value to contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Value must range from 0 to 7
  • Assembler also allows add for this instruction

ARM Equivalent

adds Rd, Rs, #Value

Example

adds r0, r3, #2  // r0 = r3 + 2 and set condition codes
                 // on the result.
adds  Rd, Rs, Rn
// Rd = Rs + Rn

Description

Add contents of Rn to contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd, Rs, and Rn must range from r0 to r7
  • Assembler also allows add for this instruction

ARM Equivalent

adds Rd, Rs, Rn

Example

adds r0, r3, r4  // r0 = r3 + r4 and set condition
                 // codes on the result.
ands  Rd, Rs
// Rd = Rd AND Rs

Description

Bitwise AND the contents of Rd and the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows and for this instruction

ARM Equivalent

ands Rd, Rd, Rs

Example

ands r0, r3  // r0 = r0 AND r3 and set condition codes
             // on the result.
asrs  Rd, Rs
// Rd = Rd >> Rs

Description

Perform arithmetic shift right on Rd by the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows asr for this instruction

ARM Equivalent

movs Rd, Rd, asr Rs

Example

asrs r0, r3  // r0 = r0 >> r3 and set condition codes
             // on the result.
asrs  Rd, Rs, #Value
// Rd = Rs >> Value

Description

Perform arithmetic shift right on Rs by a 5-bit immediate value and store the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Value must range from 0 to 31
  • Assembler also allows asr for this instruction
  • If Rd = Rs, then Rs can be omitted

ARM Equivalent

movs Rd, Rs, asr #Value

Example

asrs r2, r5, #27  // Arithmetic shift right the
                  // contents of r5 by 27 and store the
                  // result in r2.  Set conditions
                  // codes on the result.
asrs r3, #12      // same as: asrs r3, r3, #12
b     Label
// pc = Label

Description

Branch to Label.

Notes

  • Label must be within 1023 instructions

ARM Equivalent

bal Label

Example

b end  // Branch to end.
       // ... later ...
end:   // Must be half-word aligned.
bcc   Label
// if !C, pc = Label

Description

Branch to Label if C is clear (unsigned lower).

Notes

  • Label must be within 255 instructions
  • Assembler also allows blo for this instruction

ARM Equivalent

bcc Label

Example

cmp r0, #45
bcc end  // Branch to end if r0 < 45 (unsigned).
         // ... later ...
end:     // Must be half-word aligned.
bcs   Label
// if C, pc = Label

Description

Branch to Label if C is set (unsigned higher or same).

Notes

  • Label must be within 255 instructions
  • Assembler also allows bhs for this instruction

ARM Equivalent

bcs Label

Example

cmp r0, #45
bcs end  // Branch to end if r0 >= 45 (unsigned).
         // ... later ...
end:     // Must be half-word aligned.
beq   Label
// if Z, pc = Label

Description

Branch to Label if Z is set (equal).

Notes

  • Label must be within 255 instructions

ARM Equivalent

beq Label

Example

cmp r0, #45
beq end  // Branch to end if r0 = 45.
         // ... later ...
end:     // Must be half-word aligned.
bge   Label
// if N=V, pc = Label

Description

Branch to Label if N equals V (signed greater or equal).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bge Label

Example

cmp r0, #45
bge end  // Branch to end if r0 >= 45 (signed).
         // ... later ...
end:     // Must be half-word aligned.
bgt   Label
// if !Z and N=V, pc = Label

Description

Branch to Label if Z is clear and N equals V (signed greater than).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bgt Label

Example

cmp r0, #45
bgt end  // Branch to end if r0 > 45 (signed).
         // ... later ...
end:     // Must be half-word aligned.
bhi   Label
// if C and !Z, pc = Label

Description

Branch to Label if C is set and Z is clear (unsigned higher).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bhi Label

Example

cmp r0, #45
bhi end  // Branch to end if r0 > 45 (unsigned).
         // ... later ...
end:     // Must be half-word aligned.
bics  Rd, Rs
// Rd = Rd AND NOT Rs

Description

Bitwise clear the contents of Rd using the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows bic for this instruction

ARM Equivalent

bics Rd, Rd, Rs

Example

bics r0, r3  // r0 = r0 AND NOT r3 and set condition
             // codes on the result.
bl    Label
// lr = pc, pc = Label

Description

Save return address to lr, and branch to Label.

Notes

  • Label must be within 222 instructions

Example

bl routine  // Branch to routine.
            // ... later ...
routine:    // Must be half-word aligned.
mov pc, lr  // Return to previous location.
ble   Label
// if Z or N=!V, pc = Label

Description

Branch to Label if Z is set, or N equals not V (signed less than or equal).

Notes

  • Label must be within 255 instructions

ARM Equivalent

ble Label

Example

cmp r0, #45
ble end  // Branch to end if r0 <= 45 (signed).
         // ... later ...
end:     // Must be half-word aligned.
bls   Label
// if !C or Z, pc = Label

Description

Branch to Label if C is clear or Z is set (unsigned lower or same).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bls Label

Example

cmp r0, #45
bls end  // Branch to end if r0 <= 45 (unsigned).
         // ... later ...
end:     // Must be half-word aligned.
blt   Label
// if N=!V, pc = Label

Description

Branch to Label if N equals not V (signed less than).

Notes

  • Label must be within 255 instructions

ARM Equivalent

blt Label

Example

cmp r0, #45
blt end  // Branch to end if r0 < 45 (signed).
         // ... later ...
end:     // Must be half-word aligned.
bmi   Label
// if N, pc = Label

Description

Branch to Label if N is set (negative).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bmi Label

Example

cmp r0, #45
bmi end  // Branch to end if r0 - 45 has bit 31 set.
         // ... later ...
end:     // Must be half-word aligned.
bne   Label
// if !Z, pc = Label

Description

Branch to Label if Z is clear (not equal).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bne Label

Example

cmp r0, #45
bne end  // Branch to end if r0 != 45.
         // ... later ...
end:     // Must be half-word aligned.
bpl   Label
// if !N, pc = Label

Description

Branch to Label if N is clear (positive or zero).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bpl Label

Example

cmp r0, #45
bpl end  // Branch to end if r0 - 45 has bit 31 clear.
         // ... later ...
end:     // Must be half-word aligned.
bvc   Label
// if !V, pc = Label

Description

Branch to Label if V is clear (no overflow).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bvc Label

Example

cmp r0, #45
bvc end  // Branch to end if r0 - 45 didn't overflow.
         // ... later ...
end:     // Must be half-word aligned.
bvs   Label
// if V, pc = Label

Description

Branch to Label if V is set (overflow).

Notes

  • Label must be within 255 instructions

ARM Equivalent

bvs Label

Example

cmp r0, #45
bvs end  // Branch to end if r0 - 45 overflowed.
         // ... later ...
end:     // Must be half-word aligned.
bx    Rs
// pc = Rs

Description

Perform branch (plus optional state change) to address in Rs.

Bit 0 of the address determines the processor state on entry to the routine:

  • Bit 0 = 0 – causes the processor to enter ARM state
  • Bit 0 = 1 – causes the processor to enter Thumb state

Notes

  • Rs can range from r0 to r15, unlike most Thumb instructions

ARM Equivalent

bx Rs

Example

bx r11  // Transfer contents of r11 into the pc.
        // Bit 0 of r11 determines whether ARM or Thumb
        // state is entered.
cmn   Rd, Rs
// status of Rd + Rs

Description

Compare contents of Rd with the contents of -Rs.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7

ARM Equivalent

cmn Rd, Rs

Example

cmn r2, r6  // Set condition codes on r2 + r6.
cmp   Rd, Rs
// status of Rd - Rs

Description

Compare contents of Rd with the contents of Rs.

Notes

  • Sets CPSR condition codes
  • Rd and Rs can range from r0 to r15, unlike most Thumb instructions

ARM Equivalent

cmp Rd, Rs

Example

cmp r12, r6  // Set condition codes on r12 - r6.
cmp   Rd, #Value
// status of Rd - Value

Description

Compare contents of Rd with 8-bit immediate value.

Notes

  • Sets CPSR condition codes
  • Rd must range from r0 to r7
  • Value must range from 0 to 255

ARM Equivalent

cmp Rd, #Value

Example

cmp r2, #62  // Set condition codes on r2 - 62.
eors  Rd, Rs
// Rd = Rd EOR Rs

Description

Bitwise EOR the contents of Rd and the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows eor for this instruction

ARM Equivalent

eors Rd, Rd, Rs

Example

eors r0, r3  // r0 = r0 EOR r3 and set condition codes
             // on the result.
ldmia Rb!, {Rlist}
// Rlist = [Rb], increasing

Description

Load the registers specified by Rlist, starting at the base address in Rb and increasing. Write back the new base address.

Notes

  • Rlist can contain any register from r0 to r7
  • Assembler also allows for this instruction:
    • ldmfd Rb!, {Rlist}

ARM Equivalent

ldmia Rb!, {Rlist}

Example

ldmia r7!, {r0-r3}  // Load registers r0, r1, r2, r3 by
                    // starting at address in r7 and
                    // increasing.  Write back the new
                    // base address to r7.
ldr   Rd, =Value
// Rd = Value

Description

Load the 32-bit constant from the next literal pool into Rd.

Notes

  • Assembler requires a .pool statement somewhere after this instruction in order to store Value in the ROM
  • Rd must range from r0 to r7

ARM Equivalent

ldr Rd, =Value

Example

ldr r0, =123  // r0 = load 123 from pool
              // ... later ...
.pool         // outputs 123 to the ROM
ldr   Rd, [#Address]
// Rd = [Address]

Description

Load the 32-bit constant from Address into Rd.

Notes

  • Rd must range from r0 to r7
  • Address must be after the instruction within 1020 bytes, word aligned

ARM Equivalent

ldr Rd, [#Address]

Example

ldr r0, [#data]  // r0 = load 123 from data
                 // ... later ...
.align 4         // make sure data is word aligned
data: .i32 123   // outputs 123 to the ROM
ldr   Rd, [Rs]
// Rd = [Rs]

Description

Load Rd from the address in Rs.

Notes

  • Rd must range from r0 to r7
  • Rs must either range from r0 to r7, be sp, or be pc

ARM Equivalent

ldr Rd, [Rb]

Example

ldr r0, [r1]  // r0 = load from address in r1
ldr   Rd, [Rb, #Value]
// Rd = [Rb + Value]

Description

Calculate the target address by adding together the value in Rb and Value. Load Rd from the address.

Notes

  • Rd must range from r0 to r7
  • Rb must either range from r0 to r7, be sp, or be pc
  • If Rb ranges from r0 to r7, Value must range from 0 to 124, word aligned
  • If Rb is sp or pc, Value must range from 0 to 1020, word aligned

ARM Equivalent

ldr Rd, [Rb, #Value]

Example

ldr r0, [r1, #8]  // r0 = load from r1 + 8
ldr   Rd, [Rb, Ro]
// Rd = [Rb + Ro]

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Load the contents of the address into Rd.

Notes

  • Rd, Rb, and Ro must range from r0 to r7

ARM Equivalent

ldr Rd, [Rb, Ro]

Example

ldr r0, [r1, r6]  // r0 = [r1 + r6]
ldrb  Rd, [Rs]
// Rd = byte [Rs]

Description

Load the byte value at the address Rs into Rd.

Notes

  • Rd and Rs must range from r0 to r7
  • High 24 bits of Rd will be set to 0

ARM Equivalent

ldrb Rd, [Rb]

Example

ldrb r0, [r1]  // r0 = byte at [r1]
ldrb  Rd, [Rb, #Value]
// Rd = byte [Rb + Value]

Description

Calculate the target address by adding together the value in Rb and Value. Load the byte value at the address into Rd.

Notes

  • Rd and Rb must range from r0 to r7
  • High 24 bits of Rd will be set to 0
  • Value must range from 0 to 31

ARM Equivalent

ldrb Rd, [Rb, #Value]

Example

ldrb r0, [r1, #13]  // r0 = byte at [r1 + 13]
ldrb  Rd, [Rb, Ro]
// Rd = byte [Rb + Ro]

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Load the byte value at the address into Rd.

Notes

  • Rd, Rb, and Ro must range from r0 to r7
  • High 24 bits of Rd will be set to 0

ARM Equivalent

ldrb Rd, [Rb, Ro]

Example

ldrb r0, [r1, r6]  // r0 = byte at [r1 + r6]
ldrh  Rd, [Rs]
// Rd = halfword [Rs]

Description

Load the halfword value at the address Rs into Rd.

Notes

  • Rd and Rs must range from r0 to r7
  • High 16 bits of Rd will be set to 0

ARM Equivalent

ldrh Rd, [Rb]

Example

ldrh r0, [r1]  // r0 = halfword at [r1]
ldrh  Rd, [Rb, #Value]
// Rd = halfword [Rb + Value]

Description

Calculate the target address by adding together the value in Rb and Value. Load the halfword value at the address into Rd.

Notes

  • Rd and Rb must range from r0 to r7
  • High 16 bits of Rd will be set to 0
  • Value must range from 0 to 62, halfword aligned

ARM Equivalent

ldrh Rd, [Rb, #Value]

Example

ldrh r0, [r1, #12]  // r0 = byte at [r1 + 12]
ldrh  Rd, [Rb, Ro]
// Rd = halfword [Rb + Ro]

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Load the halfword value at the address into Rd.

Notes

  • Rd, Rb, and Ro must range from r0 to r7
  • High 16 bits of Rd will be set to 0

ARM Equivalent

ldrh Rd, [Rb, Ro]

Example

ldrh r0, [r1, r6]  // r0 = halfword at [r1 + r6]
ldsb  Rd, [Rb, Ro]
// Rd = sbyte [Rb + Ro]

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Load the signed byte value at the address into Rd.

Notes

  • Rd, Rb, and Ro must range from r0 to r7
  • High 24 bits of Rd will be set to bit 7
  • Assembler also allows ldrsb for this instruction

ARM Equivalent

ldrsb Rd, [Rb, Ro]

Example

ldsb r0, [r1, r6]  // r0 = sbyte at [r1 + r6]
ldsh  Rd, [Rb, Ro]
// Rd = shalfword [Rb + Ro]

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Load the signed halfword value at the address into Rd.

Notes

  • Rd, Rb, and Ro must range from r0 to r7
  • High 16 bits of Rd will be set to bit 15
  • Assembler also allows ldrsh for this instruction

ARM Equivalent

ldrsh Rd, [Rb, Ro]

Example

ldsh r0, [r1, r6]  // r0 = shalfword at [r1 + r6]
lsls  Rd, Rs
// Rd = Rd << Rs

Description

Perform logical shift left on Rd by the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows lsl, asls, or asl for this instruction

ARM Equivalent

movs Rd, Rd, lsl Rs

Example

lsls r0, r3  // r0 = r0 << r3 and set condition codes
             // on the result.
lsls  Rd, Rs, #Value
// Rd = Rs << Value

Description

Perform logical shift left on Rs by a 5-bit immediate value and store the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Value must range from 0 to 31
  • Assembler also allows lsl, asls, or asl for this instruction
  • If Rd = Rs, then Rs can be omitted

ARM Equivalent

movs Rd, Rs, lsl #Value

Example

lsls r2, r5, #27  // Logical shift left the contents of
                  // r5 by 27 and store the result in
                  // r2.  Set conditions codes on the
                  // result.
lsls r3, #12      // same as: lsls r3, r3, #12
lsrs  Rd, Rs
// Rd = Rd >>> Rs

Description

Perform logical shift right on Rd by the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows lsl for this instruction

ARM Equivalent

movs Rd, Rd, lsr Rs

Example

lsrs r0, r3  // r0 = r0 >>> r3 and set condition codes
             // on the result.
lsrs  Rd, Rs, #Value
// Rd = Rs >>> Value

Description

Perform logical right left on Rs by a 5-bit immediate value and store the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Value must range from 0 to 31
  • Assembler also allows lsr for this instruction
  • If Rd = Rs, then Rs can be omitted

ARM Equivalent

movs Rd, Rs, lsr #Value

Example

lsrs r2, r5, #27  // Logical shift right the contents
                  // of r5 by 27 and store the result
                  // in r2.  Set conditions codes on
                  // the result.
lsrs r3, #12      // same as: lsrs r3, r3, #12
mov   Rd, Rs
// Rd = Rs

Description

Move contents of Rs into Rd.

Notes

  • Does not set CPSR condition codes
  • Rd and Rs can range from r0 to r15, unlike most Thumb instructions
  • Either Rd or Rs (or both) must range from r8 to r15

ARM Equivalent

mov Rd, Rs

Example

mov r0, r12  // r0 = r12
movs  Rd, #Value
// Rd = Value

Description

Move 8-bit immediate value into Rd.

Notes

  • Sets CPSR condition codes
  • Rd must range from r0 to r7
  • Value must range from 0 to 255
  • Assembler also allows mov for this instruction

ARM Equivalent

movs Rd, #Value

Example

movs r0, #128  // r0 = 128 and set condition codes.
movs  Rd, Rs
// Rd = Rs

Description

Move contents of Rs into Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows mov for this instruction

ARM Equivalent

adds Rd, Rs, #0

Example

movs r0, r6  // r0 = r6 and set condition codes.
muls  Rd, Rs
// Rd = Rd * Rs

Description

Multiply the contents of Rd and the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows mul for this instruction

ARM Equivalent

muls Rd, Rd, Rs

Example

muls r0, r3  // r0 = r0 * r3 and set condition codes on
             // the result.
mvns  Rd, Rs
// Rd = NOT Rs

Description

Bitwise NOT the contents of Rs and place the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows mvn, nots, and not for this instruction

ARM Equivalent

mvns Rd, Rs

Example

mvns r0, r3  // r0 = NOT r3 and set condition codes on
             // the result.
negs  Rd, Rs
// Rd = -Rs

Description

Negate the contents of Rs and place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows neg for this instruction

ARM Equivalent

rsbs Rd, Rs, #0

Example

negs r0, r3  // r0 = -r3 and set condition codes on the
             // result.
nop
// No action

Description

No action.

ARM Equivalent

mov r8, r8

Example

nop
pop   {Rlist}
// pop Rlist, increase sp

Description

Pop the registers specified by Rlist from the stack. Increase the stack pointer sp.

Notes

  • Rlist can contain any register from r0 to r7, in addition to pc
  • Assembler also allows for this instruction:
    • lmdia sp!, {Rlist}
    • ldmfd sp!, {Rlist}

ARM Equivalent

ldmia sp!, {Rlist}

Example

pop {r0-r3, pc}  // pop r0, r1, r2, r3, and pc from stack
push  {Rlist}
// push Rlist, decrease sp

Description

Push the registers specified by Rlist onto the stack. Decrease the stack pointer sp.

Notes

  • Rlist can contain any register from r0 to r7, in addition to lr
  • Assembler also allows for this instruction:
    • stmdb sp!, {Rlist}
    • stmfd sp!, {Rlist}

ARM Equivalent

stmdb sp!, {Rlist}

Example

push {r0-r3, lr}  // push r0, r1, r2, r3, and lr on stack
orrs  Rd, Rs
// Rd = Rd OR Rs

Description

Bitwise OR the contents of Rd and the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows orr for this instruction

ARM Equivalent

orrs Rd, Rd, Rs

Example

orrs r0, r3  // r0 = r0 OR r3 and set condition codes
             // on the result.
rors  Rd, Rs
// Rd = Rd ROR Rs

Description

Bitwise rotate right the contents of Rd by the contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows ror for this instruction

ARM Equivalent

movs Rd, Rd, ror Rs

Example

rors r0, r3  // r0 = r0 ROR r3 and set condition codes
             // on the result.
sbcs  Rd, Rs
// Rd = Rd - Rs - NOT C-bit

Description

Subtract NOT C-Bit and the contents of Rs from the contents of Rd. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows sbc for this instruction

ARM Equivalent

sbcs Rd, Rd, Rs

Example

sbcs r0, r3  // r0 = r0 - r3 - NOT C-bit and set
             // condition codes on the result.
stmia Rb!, {Rlist}
// [Rb] = Rlist, increasing

Description

Store the registers specified by Rlist, starting at the base address in Rb and increasing. Write back the new base address.

Notes

  • Rlist can contain any register from r0 to r7
  • Assembler also allows for this instruction:
    • stmea Rb!, {Rlist}

ARM Equivalent

stmia Rb!, {Rlist}

Example

stmia r7!, {r0-r3}  // Store registers r0, r1, r2, r3 by
                    // starting at address in r7 and
                    // increasing.  Write back the new
                    // base address to r7.
str   Rd, [Rs]
// [Rs] = Rd

Description

Store the contents of Rd at the address Rs.

Notes

  • Rd must range from r0 to r7
  • Rs must either range from r0 to r7, or be sp

ARM Equivalent

str Rd, [Rs]

Example

str r0, [r1]  // store r0 at address r1
str   Rd, [Rb, #Value]
// [Rb + Value] = Rd

Description

Calculate the target address by adding together the value in Rb and Value. Store the contents of Rd at the address.

Notes

  • Rd must range from r0 to r7
  • Rb must either range from r0 to r7, or be sp
  • If Rb ranges from r0 to r7, Value must range from 0 to 124, word aligned
  • If Rb is sp, Value must range from 0 to 1020, word aligned

ARM Equivalent

str Rd, [Rb, #Value]

Example

str r0, [r1, #8]  // store r0 at address r1 + 8
str   Rd, [Rb, Ro]
// [Rb + Ro] = Rd

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Store the contents of Rd at the address.

Notes

  • Rd, Rb, and Ro must range from r0 to r7

ARM Equivalent

str Rd, [Rb, Ro]

Example

str r0, [r1, r6]  // store r0 at address r1 + r6
strb  Rd, [Rs]
// [Rs] = byte Rd

Description

Store the byte value in Rd at the address Rs.

Notes

  • Rd and Rs must range from r0 to r7

ARM Equivalent

strb Rd, [Rs]

Example

strb r0, [r1]  // store byte r0 at address r1
strb  Rd, [Rb, #Value]
// [Rb + Value] = byte Rd

Description

Calculate the target address by adding together the value in Rb and Value. Store the byte value in Rd at the address.

Notes

  • Rd and Rb must range from r0 to r7
  • Value must range from 0 to 31

ARM Equivalent

strb Rd, [Rb, #Value]

Example

strb r0, [r1, #13]  // store byte r0 at address r1 + 13
strb  Rd, [Rb, Ro]
// [Rb + Ro] = byte Rd

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Store the byte value in Rd at the address.

Notes

  • Rd, Rb, and Ro must range from r0 to r7

ARM Equivalent

strb Rd, [Rb, Ro]

Example

strb r0, [r1, r6]  // store byte r0 at address r1 + r6
strh  Rd, [Rs]
// [Rs] = halfword Rd

Description

Store the halfword value in Rd at the address Rs.

Notes

  • Rd and Rs must range from r0 to r7

ARM Equivalent

strh Rd, [Rs]

Example

strh r0, [r1]  // store halfword r0 at address r1
strh  Rd, [Rb, #Value]
// [Rb + Value] = halfword Rd

Description

Calculate the target address by adding together the value in Rb and Value. Store the halfword value in Rd at the address.

Notes

  • Rd and Rb must range from r0 to r7
  • Value must range from 0 to 62, halfword aligned

ARM Equivalent

strh Rd, [Rb, #Value]

Example

strh r0, [r1, #12]  // store halfword r0 at address
                    // r1 + 12
strh  Rd, [Rb, Ro]
// [Rb + Ro] = halfword Rd

Description

Calculate the target address by adding together the value in Rb and the value in Ro. Store the halfword value in Rd at the address.

Notes

  • Rd, Rb, and Ro must range from r0 to r7

ARM Equivalent

strh Rd, [Rb, Ro]

Example

strh r0, [r1, r6]  // store halfword r0 at address
                   // r1 + r6
sub   sp, #Value
// sp = sp - Value

Description

Subtract 9-bit immediate value from contents of sp and place the result in sp.

Notes

  • Does not set CPSR condition codes
  • Value must range from 0 to 508, word aligned
  • Assembler also allows for this instruction:
    • add sp, #-Value

ARM Equivalent

sub sp, sp, #Value

Example

sub sp, #64  // sp = sp - 64
subs  Rd, #Value
// Rd = Rd - Value

Description

Subtract 8-bit immediate value from contents of Rd and place the result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd must range from r0 to r7
  • Value must range from 0 to 255
  • Assembler also allows sub for this instruction

ARM Equivalent

subs Rd, Rd, #Value

Example

subs r6, #145  // r6 = r6 - 145 and set condition codes
               // on the result.
subs  Rd, Rs
// Rd = Rd - Rs

Description

Subtract contents of Rd to contents of Rn. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Assembler also allows sub for this instruction

ARM Equivalent

subs Rd, Rd, Rn

Example

subs r0, r3  // r0 = r0 - r3 and set condition codes on
             // the result.
subs  Rd, Rs, #Value
// Rd = Rs - Value

Description

Subtract 3-bit immediate value from contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7
  • Value must range from 0 to 7
  • Assembler also allows sub for this instruction

ARM Equivalent

subs Rd, Rs, #Value

Example

subs r0, r3, #2  // r0 = r3 - 2 and set condition codes
                 // on the result.
subs  Rd, Rs, Rn
// Rd = Rs - Rn

Description

Subtract contents of Rn from contents of Rs. Place result in Rd.

Notes

  • Sets CPSR condition codes
  • Rd, Rs, and Rn must range from r0 to r7
  • Assembler also allows sub for this instruction

ARM Equivalent

subs Rd, Rs, Rn

Example

subs r0, r3, r4  // r0 = r3 - r4 and set condition
                 // codes on the result.
swi   Comment
// software interrupt

Description

Perform a software interrupt. The processor jumps to the GBA BIOS, and runs the routine specified by Comment.

Notes

  • Comment must range from 0 to 255

ARM Equivalent

swi Comment

GBA Software Interrupts

Reference: GBATEK, CowBite.

  •  0 - SoftReset
  •  1 - RegisterRamReset
  •  2 - Halt
  •  3 - Stop/Sleep
  •  4 - IntrWait
  •  5 - VBlankIntrWait
  •  6 - Div
  •  7 - DivArm
  •  8 - Sqrt
  •  9 - ArcTan
  • 10 - ArcTan2
  • 11 - CPUSet
  • 12 - CPUFastSet
  • 13 - GetBiosChecksum
  • 14 - BgAffineSet
  • 15 - ObjAffineSet
  • 16 - BitUnPack
  • 17 - LZ77UnCompWRAM
  • 18 - LZ77UnCompVRAM
  • 19 - HuffUnComp
  • 20 - RLUnCompWRAM
  • 21 - RLUnCompVRAM
  • 22 - Diff8bitUnFilterWRAM
  • 23 - Diff8bitUnFilterVRAM
  • 24 - Diff16bitUnFilter
  • 25 - SoundBiasChange
  • 26 - SoundDriverInit
  • 27 - SoundDriverMode
  • 28 - SoundDriverMain
  • 29 - SoundDriverVSync
  • 30 - SoundChannelClear
  • 31 - MIDIKey2Freq
  • 32 - MusicPlayerOpen
  • 33 - MusicPlayerStart
  • 34 - MusicPlayerStop
  • 35 - MusicPlayerContinue
  • 36 - MusicPlayerFadeOut
  • 37 - MultiBoot
  • 38 - HardReset
  • 39 - CustomHalt
  • 40 - SoundDriverVSyncOff
  • 41 - SoundDriverVSyncOn
  • 42 - SoundGetJumpList

Example

swi 38  // Perform a hard reset.
tst   Rd, Rs
// status of Rd AND Rs

Description

Set condition codes based on the result of Rd AND Rs.

Notes

  • Sets CPSR condition codes
  • Rd and Rs must range from r0 to r7

ARM Equivalent

tst Rd, Rs

Example

tst r0, r3  // Set condition codes on r0 AND r3